The present invention generally relates to a semiconductor integrated circuit having emitter-coupled logic (ECL) circuits, and more particularly to a circuit for compensating for a capacitive load coupled to an interconnection (wiring) line mutually connecting ECL circuits.
An ECL circuit is used as a logic circuit capable of processing a signal at a high speed. Referring to FIG. 1, there is a conventional semiconductor integrated circuit having ECL circuits 1 coupled between a high-potential side power source line V.sub.CC and a low-potential side power source line V.sub.EE. Each of the ECL circuits 1 is composed of a differential circuit 1a and an output buffer circuit 1b. The differential circuit 1a is composed of current switch resistors R1, R2 and R3, emitter-coupled transistors Tr1 and Tr2 and a constant-current source Il. The output buffer circuit 1b is composed of an emitter follower transistor Tr3 and a constant-current source I2. A plurality of ECL circuits are cascaded.
During operation, when an input voltage Vin1 to the ECL circuit 1 illustrated on the left side of the drawing becomes higher than a reference voltage Vrefl and becomes equal to a logically high level, an output voltage Vefb of the differential circuit 1a is switched to a high level. Then, an output voltage of the output buffer circuit 1b is switched to a high level which is lower than the potential Vefb by a base-emitter voltage of the emitter follower transistor Tr3. On the other hand, when the input voltage Vin1 becomes lower than the reference voltage Vrefl and becomes equal to a logically low level, the output voltage Voutl is switched to a low level which is lower than the potential Vefb by the base-emitter voltage of the emitter follower transistor Tr3.
When the output voltage Voutl is at the high level, an input voltage Vin2 to the ECL circuit 1 of the next stage, that is, the base voltage of the transistor Tr1 is at the high level, which is higher than a reference voltage Vref2 applied to the base of the transistor Tr2 of the next stage. Thereby, an output voltage of the output buffer 1b of the ECL circuit 1 of the next stage becomes the high level. On the other hand, when the output voltage Voutl is at the low level, the input voltage Vin2 is at the low level, which is lower than the reference voltage Vref2. Thereby, the output voltage Vout2 of the output buffer circuit 1b of the next stage becomes the low level.
That is, signal transmission between the ECL circuits 1 is carried out via the output voltage Voutl. As shown in FIG. 1, a wiring load capacitor C is coupled to a wiring line L which mutually connects the ECL circuits 1. As the wiring line L is lengthened, the wiring load capacitor C increases. An increase in the wiring load capacitor C causes a delay time of the signal transmission. That is, it takes a long time to transmit the output signal between the ECL circuits. Conventionally, in order to reduce the delay time, the constant-current source I2 is designed to allow a large amount of current to pass through the emitter follower transistor Tr3. In a case where a resistor is substituted for the constant-current source I2, the resistor is designed to have a small resistance value.
Generally, each ECL circuit in a semiconductor integrated circuit consumes a large amount of electrical power, and thus a large amount of power is consumed in the entire semiconductor integrated circuit. In addition, the existence of the large wiring load capacitors C further increases the power consumption of the entire semiconductor integrated circuit.